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| %& & , . " ,# ,/ , 2 5 6 7 889 "# ! ! " # $ % & & "'() '(! '* ) (+ (* (( !# - ')'! , /- 0-1 ,/ - 3- 4' 3- 3- 3- + 9 9- 4 " # $ % #! :!;,!< 0,$= )))>>>>>> ))!>>>>>> &%'()((( 4''%& ?,@ 4''%& . 4''%& ,@ 4'%& ,@ 4''%& %& 4'%& %& invalid (( A3 %& ?,@ A3 %& . A3 %& ,@ 3 %& ,@ A3 %& %& 3 %& %& invalid (( &%& ?@ &%& . &%& ,@ & %& ,@ &%& %& & %& %& invalid + %& %& invalid ( ('%& ?,@ (( 9%& ?,@ ( 4' %& ?,@ 4' %& . ( %& ?,@ %& . + %& ?,@ + %& . ('%& ('. . %& ('%& ,@ (' ,@ %& 39B39 invalid )!)>>>>>> 3 ,@ 3 ,@ )!!>>>>>> 3 ,@ 3 ,@ !)))))))) ('&) ?,@ 4' %& ,@ %& ,@ + %& ,@ !)))))))! !))))))!) !))))))!! invalid invalid 4'%& %& %& %& (4B(B (B(B 4BB BB %& B B'CB 'CB 9B 9$B 9 %& ('%& & !)))))!)> invalid !)))))!!> ('& %& D4& %& & invalid (' 3*B3( %& invalid ('%& 3*B3( !))))!))> !))))!)!) &A*& &&& &A*%& &&%& ('%& %& % #! *+, !))))!)!! &%'()((( && (( invalid (( (' ( invalid (( ('&) ?,@ ( 4' %& ,@ ( %& ,@ + %& ,@ !))))!!)> CB(CB CB&B 3C4E invalid invalid invalid invalid !))))!!!> !)))!>>>> invalid invalid invalid 34E ?,$ invalid (' 4') ) ?,@ %&, F ?,@ %&, F invalid invalid invalid !))!))))) !))!!))!! !))!!)!>> !))!!!)>> !))!!!!>> :!;,!)= !)!>>> !!))>> !!)!>> !!!>>> (4((,/ ,$)"$- # ((E,/ ,$)"$- # (G&,/ ,$)"$- # G,/ ,H 4((,!$ (E,!$ ('%& ,@B(',@ %&BGI'%& ,@BJ?,@B&?,!$ invalid - +. 4''%& ?,@ A3%& ?,@ &%& ?,@ ('%& ?,@ 9%& ?,@ 4'%& ?,@ %& ?,@ +%& ?,@ 4''%& . A3%& . &%& . ('%& . ('. %& 4'%& . %& . +%& . 4''%& ,@ A3%& ,@ &%& ,@ ('%& ,@ 3 ,@ 3 ,@ 4'%& ,@ 3%& ,@ &%& ,@ (' ,@ %& 3 ,@ 3 ,@ / 0 ))) ))! )!) )!! - % ))) ))! )!) )!! !)) !)! !!) !!! ))) ))! )!) )!! !)) !)! !!) !!! ))) ))! )!) )!! !) !! ))) ))! )!) )!! !) !! %& ( 1 %& %& > :0,)= :0,)= 2 3 / 0 :/,)= - % ( %& :0,)= - +. *+, 4''%& %& A3%& %& &%& %& 39B39 4'%& %& 3%& %& &%& %& K K 4'%& %& %& %& +%& %& K 4(A! 4(A$ K ('& %& ('%& & D4&%& & ('3( %& ('3* %& &A*& &&& K &A*%& &&%& ('%& %& ('%& 3( ('%& 3* && ('.( ('.(M K / 0 !)) - % ))) ))! )!) )!! ))) ))! )!) )!! ))) ))! )!) )!! ))) ))! ( 1 2 3 / 0 - % 4(A! 4(A$ >>> & & & ( %& )))))) %& )))))! ))))!) ))))!! )))!) )))!! ))!)) ))!)!) ))!)!! ) ! > > %& %& >> %& %& %& %& >> >> >> %& %& %& %& >> )!)L)!! ))) ))! )!) )!! ))) ))! )!)L)!! ))) ))! )!) )!! ))) )!) ))! )!! ) ! & & >>> > > %& %& %& ) ! > > >> > > >> - +. *++, 9'! K K 4') ?,@ ) ?,@ 34E?,$ K (4(( ,$) ((E ,$) (G& ,$) ('&) ?,@ 4'%& ,@ %& ,@ +%& ,@ G ,H 4((,!$ (E,!$ ('%& ,@ (',@ %& GI'%& ,@ J?,@ &?,!$ /- % !)) !)! !!) !!! ) ! ))) ( 1 >> >> >> 2 3 / ))!!) 0 - % >>> ( % 4+ L 9'! >>>>>> :;,)= ))!L)!! ))) ))! )!) )!! >>>> )) )! !) !! )! > :0,1= :0,1= >> :!,)= >>> :!;,)= L !)))))))-!!))!!!! !!)! :!H,!1= 99:0,)= 4':0,)= :0,)= :!!,)= &) %& ) ! ) ! )) )! !) !! %& %& %& >> :0,)= :!!,)= ! " #$%&'( )*+ ,-". / 0 +5 + 67 *8+59, :7 ') '! + ) ! >)'*,'() >!'*,'(! ;! / +5 #+6 + 67 *87+9, :7 .'>M ,; .:'>- ,;= .:'>M ,;=O .:'>- ,;=O + )) )! !) !! < '9:'>= '>'>M '9:'>M"$N ,;#= '>'>M"$N ,;# '9:'>M = '>'> '9:'>M"$N ,;#= '>'> 0 1( 23 / 242(562(( 789 562(( 789: (( 78 . ( ( ( #(( 6;7<9' = 562<9 562<9: 562><9 562><9: 1 3 + + 67 *89, :7 *'0, 3F A( A%C ICR IC S A(C A% I& 9 &( I U C)-C$ + )))) )))! ))!) ))!! )!)) )!)! )!!) )!!! !))) !))! !)!) !)!! !!)) !!)!-!!!! P) P! Q IP! Q IP) Q SP! K - K 65I Q 26I P) T K P! K 626I K I5 T K FU C:)=P!BC:!=P!BC:$=P! < ?067<9 #0&2@0 . (A' 8 "!9 + 67 :7 (4 ( ( ( 4 + ))) ))! )!) )!! !)) !)! !!) !!! < 2 8 "!%9 + 67 :7 'C 'C 9 9$ 9 L + ))) ))! )!) )!! !)) !)! !!) !!! !N $N !N K < 1 8#;!9 + 67 :7 (C C C & 3C4E L L L + ))) ))! )!) )!! !)) !)! !!) !!! ( * " *# K K K K < ="> < ! 4' + 4'' A3 & 4' 3 & 9 3 3 3 3 39B39 &A* && &A* && && (4 ( ( ( 4 'C 'C 9 9$ 9 L %& L L & L L %& L L %& < %& %& ,@ ! %& !% ,@ %& . ?,@ !!5$ !!7$ !!M$ !!M6$M! !M6$M! !!M$M !!M6$M !M6$M ?,@ !2$ ,@ !"$: =!# !"$: =)# !6"$: =# T6"$: =# U!B) *:=%& "M!# %&*:-!= "-!# *:=& "M!# &*:-!= "-!# L$ !:0= !V!:1,)= )W !:0= !V!:1,)= )W !:0= !V!:1,)= W :0= !V!:1,)= !:0=W :)= !V!:0= !:0,!=W !:)= !V) !:0,!=W !:)= !V !:0,!=W !:)= !V!:)= !:0,!=W !!M! !!M !!M)UU !!M)UUM !6! !6!M! !6!M L T K T T T T T T T T K T K T K T K T T K T K < !!2$ <. T T T T K T K T K T K T K T K T T T T T L L T L ? 6 4+ @ : !D! ="> < *+, ! (' (' (' ! %& , F &) %& !% %& , F ?,@ !$ !$ < <. T L T ? 6 4+ @ : !D! %& !$ & ,@ . ?,@ 3*B3( %& %& %& L ?,@ L & L !$ !$ !$ "3*,3(#&9:"(+,(*,((#= ((MM.(M ))2$ ))5$ ):/,<=$ !$ $!" > )B!# F +4E *:!;,)=V&:!;,!$= &:!!,)=M$W &! &:!!,)=&:!!,)=M$ F (:!H,)=V&:!H,!$= &:!!,)=M$W &! &:!!,)=&:!!,)=M$ +4E *:!;,)=V&:!;,!$= &:!!,)=M!W &:!!,)=! (:!H,)=V&:!H,!$= &:!!,)=M!W &:!!,)=! "PP)#&&: =-$N ,@ -- &&: =MM -- F &! &:!!,)=&:!!,)=M$ F &:!!,)=&:!!,)=M! &:!!,)=&:!!,)=M! (' (' (' (' 4' 34E D4& (4(( & 3*B3( ,@ . .( .(M ) ?,$ %& ,$) L L L L L L L L !D$ !D! $D$ ((E ,$) L L 4(( (E GI' ,!$ ,!$ L L ,@ L L L !D$ (G& G ,$) ,H L L L L $D$ !D$ B0B 01 B0B 01 B0 B 01 &( )*+,-".$%& ="> < *++, ! (C C C & 3C4E J (' (' & ?,@ ,@ %& ?,!$ L %& ,@ L ! L !% L &(:!H,)= &*:-$= "-$# &*:-$= "-$# & J&:0,)= J' !$ J&:0,)= ('' ('D !$ J&:0,)= ('' ('D J&:!!,)= &' L L T L < <. L ? 6 4+ @ : !D$ !D$ !D$ !D! !D! !D! - / B0B 01 B0B 01 % C @0=D&0= 0 1(/ C @%D23? 0EA / C ?2D2 ? C )%D3*FD0G33 2()&D3*F@D0G33@ #A ' / (0G33D3*F )%D3*FD0G33 )&D3*F@D0G33@-/ )%D3*FD0G33 3)%D33*FD30G33#A ' " "$ "## " " X4(AY 4(A 4(A K !"!# "# T "I# K "S# K "# "! $A +'2 & 4(A K %& K '9: ,@= %& 4(AP4'' A3 & 4' + UA3 & %&M"'9: ,@=#M! ,@ ) K '*" >'9 * 3 # K )")# %&%&4(A'9:)), ,@= P) %&%&4(A'9:'*, @= P! @- 4'') @) "! $A ?77'2 4(A %& @- K %& 4(AP4'' A3 & 4' + UA3 & %&M"?,@#M! ?,@@- K %&%&4(A?,@ 4'') ?04 BB))M04 BB4 P! '*P)!* BB))M'9:)!@)= "! $+A $ 4(A%& %& %& 4(AP4'' A3 & 4' + UA3 & %& M"%&#M! %& %& %& %& 4(A%& %& -%& 4(AP&"# 4'') ! BB))M! "! $A B+7 & 4(A K %& '9:'= %& > ''*,'( "'*,'()'*,'(!# 4(AP4'' A3 & 4' + UA3 & %&M"'9: =#M! P'>M,; :'>- ,;= :'>M ,;=O :'>- ,;=O "'>P')'!# %&-'9: = 4(AP&"# %&%&4(A'9:'>= '>'>M ,; P'>M ,; %&%&4(A'9:'>- ,;= '>'>- ,; P:'>- ,;= %&%&4(A'9:'>M ,;= P:'>M ,;=O %&%&4(A'9:'>- ,;= P:'>- ,;=O D '("- - # '* 4'') .')M$ 4'') .:')-$= 4'') .:'!M$=O 4'') .:'!-$=O BB ')P)$UU BB))M'9:)$UU= '*)< '())! BB ')P)$)! BB))M'9:)!UU= '*)! '()UU BB '!P)$UU BB))M'9:)<)!= '*)$ '(!UU BB '!P)$)) BB))M'9:)!UC= '*)$ '(!)) "! $+A $ & 4(A%& %& %& 4(AP4' 3 & %& %& %& %& M%&M 4(AP4' %& %& M"%&#M 4(AP3 %& M"%&#M 4(AP&"# 4'') $ 4'! < A3) $ 3! < &) $ &! < BB !,) <,$ !1- BB !1- 4'' 4' BB !,) <,$ !1- BB !1- A3 3 BB !,) <,$ !1- BB !1- & & "! $A +'2 & 4(A%& '9: ,@= %&%&M'9: ,@=M 4(AP4' %&%&M"'9: ,@=#M 4(AP3 %&M"'9: ,@=#M 4(AP&"# $! $ *7!7 ! &(P9 9$ 9 9%& 9$%& 9%& %&" # %&M!"$N %&# %&M" %&# 9$) 9! BB !,)!1- BB9$ 9 $N ; $ *7@;7 !, ' P 'C 'C %& %& 'C%& 'C%& %& %&%&M! %&P! %&%&M ' %& %&%&MUU ' %&P) %&%&MUUM ) ! 'C) 'C! BB !,)!1- BB !,) BB !,)!1- BB !,) 'C 'C C< @ " " #" # K ! ' !"!# "# I "I# K "S# K "# $ "# 93%& K "# 93%& K "S# I "I# ! ) $ "# 93%& K "# 93%& K "S# ! 93 I ! ) $ "# 93%& K "# 93%& B K "S# I "I# ! ) $ "# 93%& K "# 93%& K "S# I "I# ! ) $ "# (3%& K "# 93%& K "S# I "I# ! ) $ "# (3%& K "# 93%& K "S# I ! ) $ "# (3%& K "# 93%& K "S# I "I# ! ) $ "# (3%& K "# 93%& K "S# I "I# ! ) ; " ( K 4 K I "I# K "# !"!# )) 93 ! K ; $A +'2 ( K '9: ,@=%&4 ,@ K ) ")# %&'9:)), ,@= P) %&'9:'*, ,@= P! @- (') @) BB P! '*P)!* BB)'9:)!@)= ; $A B+7 ( K . %& P'>M,; :'>- ,;= :'>M ,;=O :'>- ,;=O "'>P')'!# %&'9:'>= '>'>M ,; P'>M ,; %&'9:'>- ,;= '>'>- ,; P:'>- ,;= %&'9:'>M ,;= P:'>M ,;=O %&'9:'>- ,;= P:'>- ,;=O D '("- - # '* (') .:')M)<=O BB '*,'()P)$0) BB)'9:)$0<= '*,'())$0) ; A ?77'2 ( @- K C%C% %&&) -'*" >' 9 * 3 # '()" >'9 ( 3 #B'(! ) ")#?,@@- K C%?,@ (')?04 (''* ?)< BB)04 BB'*)< ; $''%A $''% ( K F F ('),! $,< BB) F! $ F< ; $A DC@ D ( K 3*3(%&3* 3( @- >K (' (' ('%& 3*B3(K %& %&3*"3(# ('.( (') 3* ('! 3( BB .(+,(*,(( ; DC@ DA $ ( K %&3*3( K K K 3*B3( 3*"3(#%& ; $A $ ( K &%& %&& (') '* BB)'* ; $A $ ( K %&& &%& ; +'2A $ K %& "'9# ,@ K )")# '9:)), ,@=%& P) '9:'*, ,@=%& P! (''* ) BB'*) @- ('04 ) BB P! '*P)$ BB'9:)$04=) ; B+7A $ ( K . %& P'>M,; :'>- ,;= :'>M ,;=O :'>- ,;=O "'>P')'!# '9:'>=%& '>'>M ,; P'>M ,; '9:'>- ,;=%& '>'>- ,; P:'>- ,;= '9:'>M ,;=%& P:'>M ,;=O '9:'>- ,;=%& P:'>- ,;=O D '("- - # '* ('.:')M)<=O ) BB '*,'()P)!0) BB'9:)!0<=) '*,'())!0) D C " 3 T Z F 4Z K & K "X Y# & F F K & F ( C $- $)- Z E '0A 77'1 ,H "$N # & "&:!H,!$=,"&:!!,)=M,H## &:!!,)=&:!!,)=M,H &:!!,)=&:!!,)=M! F " ,/ K # (!@/!!, GI !)0 BB &P!@/!! BB >&!@;!@"!@/!!M!)0#I "I# E$ '0A 77'%( G ,$)T 1/E &:!H,!1= &:!;,)=:!;,)= F T 1/E &:!H,)=:!H,)= F T Q1/E &:!!,)=&:!!,)=M! (!@/!!, (G&I !)!)0 BB &P!@/!! BB >N&!)!)0I "I# EF; A 77'2 G ,@ K F< T GI' F Z K GI' > GI'F "PP)#&&: ="-#$N ,@ -! &&: =M! -! (&[4, * * * BB GI') (&[4BBZ F(&[4)T 4''! ?$ BB > " # 77'% K & F"X Y&# Z ,!$ &:!H,!$= !- F"&M!#&1/ED &K &:!H,!1=K F *:=:!;,)= &M! M$"F# *:=:!H,)= &M! M$"F# &:!!,)=,!$ &1/EDP) &1/EDP! (!@/!!, 4((!)0 BB &P!@/!! BB !@!)0 & BB F"*!@/!$#&1/EDP! '0A 77'%( K & F" &# Z ,$) $- K F"&M$#&1/ED &K ))))!!!!!!&:!H,!1=K F &:!H,!1= :!H,!1= *:=:!;,)= &M$ M$"F# F &1/EDP) *:=:!H,)= &M$ M$"F# F &1/EDP! &:!;,)=:!;,)= F &1/EDP) &:!H,)=:!H,)= F &1/EDP! &:!!,)=&:!!,)=M$ (!@/!!, (4((I !),!)0 BB &P!@/!! BB !)!)0 & BB F"*!@/!<# > 77'% K &( Z ,!$ &:!H,!$= !- K ("&M!# T 1/E &K &:!H,!1=K (+ (:!;,)= &M! (:!H,)= &M! &:!!,)=,!$ T 1/E T Q1/E (!@/!!, (E!)0 BB &P!@/!! BB !@!)0 &K BB("(:!H,)=!@/!$#T 1/E > '0A 77'%( K &( Z ,$) $- K ("&M$# T 1/E &K &:!H,!1= K (+ (:!;,)= &M$ F T 1/E (:!H,)= &M$ F T 1/E &:!;,)=:!;,)= F T 1/E &:!H,)=:!H,)= F T 1/E &:!!,)=&:!!,)=M$ (!@/!!, ((EI !),!)0 BB &P!@/!! BB !)!)0 &K BB("(:!H,)=!@/!<#T 1/E A C "):!=# T 1/E &:!H,!1= *:!H,!1= &:!;,)=*:-$= -$"F#T 1/E &:!H,)=*:-$= -$"F#T 1/E C BB P< *:!=P!@/)0 BB >& !@/)0 ! F ( T 1/E &:!H,!1= (+ &:!;,)=(:!;,)= &:!H,)=(:!H,)= T 1/E T 1/E (C B (P!@/)0 B B > > &P!@/)0 B BBT 1/E E$@>@ G&B(EB4(( GB(EB4(( "! # 4((B(E G&B(EB4(( GB(EB4((F G&B(EB4(( (G&B((EB(4(("$ # D # $" " D ! +'2 & K ,@ < %& F F K U 3P3 3 3 3 3, 3, 3, 3, "< # , )-0 <'9:)), ,@=3 P) <'9:'*, ,@=3 P!" 3# I "I# ) 3$;< 3$;< BB P) <'9:)),$;= < BB F <'9:)),$;= P) D#@D# U 3D U 3 <"> #\ U F U) U! "39# "39# # $A ?77'2 & 4' %& ,@ I "I# K "# %& I %&2?,@ D ! $ & %& %& QK K %& ?,@ 4'%& ?,@ +%& ?,@ NK ; (A ?77'2@ (A ?77'2 B ) F) ))2?,@ ))5?,@ D > ?77'% ( ):/,<=?:!,)= ):/,<=?:!,)= # " " $ $A $ K %& &) ! K %& & &%& %& $"C K C% F"& C%F# C%P%& & *:=:0,)=C% M! &A*) BB )P)@ P$ BB *:$=:0,)=)@ < D4&) '* BB '*P)) )P)@ BB '*P)@ )P)) $$ &FC% C%P%& & C%*:-!=:0,)= L! $$ &$ F $ ' F & ! D > ' & D > F & ?77'2 ' & ! J&:0,)= J' ; $A 77'2 %&",@# J&:0,)= ('' ('D ; 77'2A $ ",@#%& J&:0,)= ('' ('D $ ?77'% % J&:!!,)= &' &&) BB P< *:$=P!@/)0 BB))0 $ ; ( :3*,3(=&9:(+,(*,((= :3*,3(=&9:(+,(*,((= ((MM "('.(# "('.(M# 3* 3( ('%& 3(B3* ('(+ ! ('(* $ ('(( < ('.( BB !,$,< BB ."(+,(*,((#3*,3( $"; " @; C> )) ?))))))!) "C# )4') ?!!!!!!)! "'# C> C )! ' ' * * * C <@< &) ) 4') ) "U# "U# U !) U U U $@; 9A K J?)4 J?); "&# "'(C# & &AF F & '(C &AF F &"'(C# & & & * * * Format: ADC Operation: Flags: . Example: ADC ADC ADD ADC R0, 80h R0, R1 R0, R2 R1, R3 // If eid = 0, R0 R0 + DM[0080h] + C // If eid = 1, R0 R0 + DM[IDH:80h] + C // R0 R0 + R1 + C In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. Even if the result of "ADD R0, R2" is not zero, Z flag can be set to `1' if the result of "ADC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit addition, take care of the change of Z flag. Format: ADD Given: IDH:IDL0 = 80FFh, eid = 1 ADD ADD ADD ADD ADD ADD ADD R0, 80h R0, #12h R1, R2 R0, @ID0 + 2 R0, @[ID0 - 3] R0, @[ID0 + 2]! R0, @[ID0 - 2]! // R0 R0 + DM[8080h] // R0 R0 + 12h // R1 R1 + R2 // R0 R0 + DM[80FFh], IDH 81h, IDL0 01h // R0 R0 + DM[80FCh], IDH 80h, IDL0 FCh // R0 R0 + DM[8101h], IDH 80h, IDL0 FFh // R0 R0 + DM[80FDh], IDH 80h, IDL0 FFh In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Format: AND In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data memory DM[0051h-007Fh] are not mapped in S3CB205/FB205. In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Format: Operation: AND SR0, #imm:8 SR0 SR0 & imm:8 AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the result in SR0. Flags: Example: - Given: SR0 = 11000010b nIE nIE0 nIE1 EQU EQU EQU AND AND ~02h ~40h ~80h SR0, #nIE | nIE0 | nIE1 SR0, #11111101b In the first example, the statement "AND SR0, #nIE|nIE0|nIE1" clear all of bits of the global interrupt, interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to `1' by instruction "OR SR0, #imm:8". Refer to instruction OR SR0 for more detailed explanation about enabling bit. In the second example, the statement "AND SR0, #11111101b" is equal to instruction DI, which is disabling interrupt globally. Format: Operation: Flags: BANK #imm:2 SR0[4:3] imm:2 - For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3. BANK LD BANK LD #1 R0, #11h #2 R1, #22h // Select register bank 1 // Bank1's R0 11h // Select register bank 2 // Bank2's R1 22h Example: Format: BITC adr:8.bs bs: 3-digit bit specifier Operation: Flags: R3 ((adr:8) ^ (2**bs)) (adr:8) ((adr:8) ^ (2**bs)) if (TF == 0) if (TF == 1) BITC complements the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = FFh, eid = 1 BMC BITC BMS BITC 80h.0 80h.1 // TF 0 // R3 FEh, DM[0180h] = FFh // TF 1 // DM[0180h] FDh Example: Format: BITR adr:8.bs bs: 3-digit bit specifier Operation: Flags: R3 ((adr:8) & ((11111111) - (2**bs))) (adr:8) ((adr:8) & ((11111111) - (2**bs))) if (TF == 0) if (TF == 1) BITR resets the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = FFh, eid = 1 BMC BITR BMS BITR 80h.1 80h.2 // TF 0 // R3 FDh, DM[0180h] = FFh // TF 1 // DM[0180h] FBh Example: Format: BITS adr:8.bs bs: 3-digit bit specifier. Operation: Flags: R3 ((adr:8) | (2**bs)) (adr:8) ((adr:8) | (2**bs)) if (TF == 0) if (TF == 1) BITS sets the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = F0h, eid = 1 BMC BITS BMS BITS 80h.1 80h.2 // TF 0 // R3 0F2h, DM[0180h] = F0h // TF 1 // DM[0180h] F4h Example: Format: BITT adr:8.bs bs: 3-digit bit specifier. Operation: Z ~((adr:8) & (2**bs)) BITT tests the specified bit of a value read from memory. Flags: Example: Z: set if result is zero. Reset if not. Given: DM[0080h] = F7h, eid = 0 BITT JR * * * 80h.3 Z, %1 // Z flag is set to `1' // Jump to label %1 because condition is true. %1 BITS NOP * * * 80h.3 Format: Operation: !" # BMS/BMC BMC/BMS clears (sets) the TF bit. TF 0 if BMC TF 1 if BMS TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR, and BITS. Flags: - BMC/BMS are the only instructions that modify the content of the TF bit. BMS BITS BMC BITR LD // TF 1 81h.1 // TF 0 81h.2 R0, R3 Example: $"$ %$&$' Format: CALL cc:4, imm:20 CALL imm:12 ! 2(0G33@ / #7;'0G33 0G33@#A '-/ 0G33 30G33#A ' Example: CALL * * * C, Wait // HS[sptr][15:0] current PC + 2, sptr sptr + 2 // 2-word instruction // HS[sptr][15:0] current PC + 1, sptr sptr + 2 // 1-word instruction // Address at 0088h CALL * * * 0088h Wait: NOP NOP NOP NOP NOP RET $"$ Format: Operation: CALLS imm:12 HS[sptr][15:0] current PC + 1, sptr sptr + 2 if the program size is less than 64K word. HS[sptr][19:0] current PC + 1, sptr sptr + 2 if the program size is equal to or over 64K word. PC[11:0] imm:12 CALLS unconditionally calls a subroutine residing at the address specified by imm:12. Flags: Example: - CALLS * * * Wait Wait: NOP NOP NOP RET Because this is a 1-word instruction, the saved returning address on stack is (PC + 1). ( Format: CLD imm:8, EQU EQU EQU EQU * * * 00h 01h 02h 03h CLD CLD CLD CLD AH, R0 AL, R1 BH, R2 BL, R3 // A[15:8] R0 // A[7:0] R1 // B[15:8] R2 // B[7:0] R3 The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816. Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816. ( ) Format: Operation: Flags: Example: CLD EQU EQU EQU EQU * * * 00h 01h 02h 03h CLD CLD CLD CLD R0, AH R1, AL R2, BH R3, BL // R0 A[15:8] // R1 A[7:0] // R2 B[15:8] // R3 B[7:0] The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816. Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816. *+ Format: COM Z: set if result is zero. Reset if not. N: set if the MSB of result is 1. Reset if not. Given: R1 = 5Ah COM R1 // R1 A5h, N flag is set to `1' ,+ Format: COM2 Example: Given: R0 = 00h, R1 = 5Ah COM2 COM2 R0 R1 // R0 00h, Z and C flags are set to `1'. // R1 A6h, N flag is set to `1'. Format: COMC Example: If register pair R1:R0 is a 16-bit number, then the 2's complement of R1:R0 can be obtained by COM2 and COMC as following. COM2 COMC R0 R1 Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register pair R1: R0 has value of FF01h, then 2's complement of R1: R0 is made of 00FFh by COM2 and COMC. At this time, by instruction COMC, zero (Z) flag is set to `1' as if the result of 2's complement for 16-bit number is zero. Therefore when programming 16-bit comparison, take care of the change of Z flag. Format: Operation: Flags: Example: COP #imm:12 COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals. - COP COP #0D01h #0234h // generate 1 word instruction code(FD01h) // generate 1 word instruction code(F234h) The above two instructions are equal to statement "ELD A, #1234h" for MAC816 operation. The microcode of MAC instruction "ELD A, #1234h" is "FD01F234", 2-word instruction. In this, code `F' indicates `COP' instruction. Format: CP Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1 CP CP CP R0, 80h R0, #73h R0, R1 R1, @ID0 R1, @[ID0 - 5] R2, @[ID0 + 7]! R2, @[ID0 - 2]! // C flag is set to `1' // Z and C flags are set to `1' // V flag is set to `1' // Z and C flags are set to `1' CP CP CP CP In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Format: CPC If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC to compare two 16-bit numbers as follows. CP CPC R0, R1 R2, R3 Because CPC considers C when comparing Format: DEC Example: Given: R0 = 80h, R1 = 00h DEC DEC R0 R1 // R0 7Fh, C, V and N flags are set to `1' // R1 FFh, N flags is set to `1' Format: DECC Example: If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to decrement 16-bit number as follows. DEC DECC R0 R1 Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag. "&$%$&$' Format: Operation: Flags: Example: DI Disables interrupt globally. It is same as "AND SR0, #0FDh" . DI instruction sets bit1 (ie: global interrupt enable) of SR0 register to "0" - Given: SR0 = 03h DI // SR0 SR0 & 11111101b DI instruction clears SR0[1] to `0', disabling interrupt processing. - "&$%$&$' Format: Operation: Flags: Example: EI Enables interrupt globally. It is same as "OR SR0, #02h" . EI instruction sets the bit1 (ie: global interrupt enable) of SR0 register to "1" - Given: SR0 = 01h EI // SR0 SR0 | 00000010b The statement "EI" sets the SR0[1] to `1', enabling all interrupts. &. %$&$' Format: Operation: IDLE The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt or reset operation. The IDLE instruction is a pseudo instruction. It is assembled as "SYS #05H", and this generates the SYSCP[7-0] signals. Then these signals are decoded and the decoded signals execute the idle operation. - (23? *% ( 23? Flags: Example: IDLE NOP NOP NOP * * * The IDLE instruction stops the CPU clock but not the system clock. & Format: INC Example: Given: R0 = 7Fh, R1 = FFh INC INC R0 R1 // R0 80h, V flag is set to `1' // R1 00h, Z and C flags are set to `1' & Format: INCC If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment 16-bit number as following. INC INCC R0 R1 Assume R1:R0 is 0010h, statement "INC R0" increase R0 by one without carry and statement "INCC R1" set zero (Z) flag to `1' as if the result of 16-bit increment is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit increment, take care of the change of Z flag. $)&$/ 0 Format: Operation: Flags: IRET PC HS[sptr - 2], sptr sptr - 2 IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation. - The program size (indicated by the nP64KW signal) determines which portion of PC is updated. When the program size is less than 64K word, only the lower 16 bits of PC are updated (i.e., PC[15:0] HS[sptr - 2]). When the program size is 64K word or more, the action taken is PC[19:0] HS[sptr - 2]. Example: SF_EXCEP: NOP * * * // Stack full exception service routine IRET 1$2 Format: JNZD - Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however, that the chosen instruction should be "dead" outside the loop for it executes even when the loop is exited (i.e., JNZD is not taken). Given: IDH = 03h, eid = 1 BANK LD LD LD JNZD LD * * * Example: %1 #3 R0, #0FFh R1, #0 IDL0, R0 R0, %B1 @ID0, R1 // R0 is used to loop counter // If R0 of bank3 is not zero, jump to %1. // Clear register pointed by ID0 This example can be used for RAM clear routine. The last instruction is executed even if the loop is exited. 1$%$&$' Format: Operation: JP cc:4 imm:20 JP cc:4 imm:9 If JR can access the target address, JP command is assembled to JR (1 word instruction) in linking time, else the JP is assembled to LJP (2 word instruction) instruction. There are 16 different conditions that can be used, as described in table 7-6. LD * * * Example: %1 R0, #10h // Assume address of label %1 is 020Dh JP JP * * * Z, %B1 C, %F2 // Address at 0264h // Address at 0265h %2 LD * * * R1, #20h // Assume address of label %2 is 089Ch In the above example, the statement "JP Z, %B1" is assembled to JR instruction. Assuming that current PC is 0264h and condition is true, next PC is made by PC[11:0] PC[11:0] + offset, offset value is "64h + A9h" without carry. `A9' means 2's complement of offset value to jump backward. Therefore next PC is 020Dh. On the other hand, statement "JP C, %F2" is assembled to LJP instruction because offset address exceeds the range of imm:9. 1$ 3 Format: JR cc:4 imm:9 cc:4: 4-bit condition code Operation: PC[11:0] PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign-extended to 12 bits when added to PC. There are 16 different conditions that can be used, as described in table 7-6. - Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to compute the actual jump address, while LJP directly jumps to imm:20, the target. JR * * * Flags: Example: Z, %1 // Assume current PC = 1000h %1 LD * * * R0, R1 // Address at 10A5h After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to `1'. The range of the relative address is from +255 to -256 because imm:9 is signed number. $"$ Format: Operation: LCALL cc:4, imm:20 HS[sptr][15:0] current PC + 2, sptr sptr + 2, PC[15:0] imm[15:0] if the condition holds and the program size is less than 64K word. HS[sptr][19:0] current PC + 2, sptr sptr + 2, PC[19:0] imm:20 if the condition holds and the program size is equal to or over 64K word. PC[11:0] PC[11:0] + 2 otherwise. LCALL instruction is used to call a subroutine whose starting address is specified by imm:20. Flags: Example: - LCALL LCALL L1 C, L2 Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word instruction, the saved returning address on stack is (PC + 2). ( 4 Format: LD adr:8, If eid bit of SR0 is zero, the statement "LD 80h, R0" load value of R0 into DM[0080h], else eid bit was set to `1', the statement "LD 80h, R0" load value of R0 into DM[0180h] ( 4 &5 Format: LD @idm, In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) ( 0 Format: LD In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) ( 6" 76" Format: LD R2:1, R0:3 R0:0, R0:2 // Bank1's R2 bank3's R0 // Bank0's R0 bank2's R0 ( 7 /# ( Format: LD ( /# (7 Format: LD ( Format: LD ( & Format: Operation: LD SPR0, #imm:8 SPR0 imm:8 LD SPR0 loads an 8-bit immediate value into SPR0. Flags: Example: - Given: eid = 1, idb = 0 (index register bank 0 selection) LD LD LD LD IDH, #80h IDL1, #44h IDL0, #55h SR0, #02h // IDH point to page 80h The last instruction set ie (global interrupt enable) bit to `1'. Special register group 1 (SPR1) registers are not supported in this addressing mode. ( Format: Operation: LDC ILX, R1 ILH, R2 ILL, R3 @IL R1, TBH R0, TBL // Loads value of PM[ILX:ILH:ILL] into TBH:TBL // Move data in TBH:TBL to GPRs for further processing The statement "LDC @IL" do not increase, but if you use statement "LDC @IL+", ILL register is increased by one after instruction execution. 1$ Format: LJP cc:4, imm:20 cc:4: 4-bit condition code Operation: PC[15:0] imm[15:0] if condition is true and the program size is less than 64K word. If the program is equal to or larger than 64K word, PC[19:0] imm[19:0] as long as the condition is true. There are 16 different conditions that can be used, as described in table 7-6. - LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address of the jump. LJP * * * Flags: Example: C, %1 // Assume current PC = 0812h %1 LD * * * R0, R1 // Address at 10A5h After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true. ($"$ Format: LLNK cc:4, imm:20 cc:4: 4-bit condition code Operation: If condition is true, IL[19:0] {PC[19:12], PC[11:0] + 2}. Further, when the program is equal to or larger than 64K word, PC[19:0] imm[19:0] as long as the condition is true. If the program is smaller than 64K word, PC[15:0] imm[15:0]. There are 16 different conditions that can be used, as described in table 7-6. Flags: - LLNK is used to conditionally to call a subroutine with the return address saved in the link register (IL) without - This is a 2-word instruction. LLNK NOP * * * Example: Z, %1 // Address at 005Ch, ILX:ILH:ILL 00:00:5Eh // Address at 005Eh %1 LD * * * R0, R1 LRET ($"$ %$&$' Format: Operation: LNK cc:4, imm:20 LNK imm:12 If LNKS can access the target address and there is no conditional code (cc:4), LNK command is assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2 word instruction). LNK LNK NOP * * * * * * Example: Z, Link1 Link2 // Equal to "LLNK Z, Link1" // Equal to "LNKS Link2" Link2: NOP LRET Subroutines section CODE, ABS 0A00h Subroutines Link1: NOP * * * LRET ($"$ Format: Operation: Flags: LNKS imm:12 IL[19:0] {PC[19:12], PC[11:0] + 1} and PC[11:0] imm:12 LNKS saves the current PC in the link register and jumps to the address specified by imm:12. - LNKS is used to call a subroutine with the return address saved in the link register (IL) without - Example: LNKS NOP * * * Link1 // Address at 005Ch, ILX:ILH:ILL 00:00:5Dh // Address at 005Dh Link1: NOP * * * LRET $)($"$ Format: Operation: Flags: LRET PC IL[19:0] LRET returns from a subroutine by assigning the saved return address in IL to PC. - Example: LNK Link1: NOP * * * Link1 LRET ; PC[19:0] ILX:ILH:ILL . Format: Operation: NOP No operation. When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction time is delayed by approximately one machine cycle per each NOP instruction encountered. Flags: Example: - NOP . Format: OR In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) . Format: Operation: OR SR0, #imm:8 SR0 SR0 | imm:8 OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0. Flags: Example: - Given: SR0 = 00000000b EID IE IDB1 IE0 IE1 EQU EQU EQU EQU EQU OR OR 01h 02h 04h 40h 80h SR0, #IE | IE0 | IE1 SR0, #00000010b In the first example, the statement "OR SR0, #EID|IE|IE0" set global interrupt(ie), interrupt 0(ie0) and interrupt 1(ie1) to `1' in SR0. On the contrary, enabled bits can be cleared with instruction "AND SR0, #imm:8". Refer to instruction AND SR0 for more detailed explanation about disabling bit. In the second example, the statement "OR SR0, #00000010b" is equal to instruction EI, which is enabling interrupt globally. . Format: Operation: POP sptr sptr - 2 POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated. Flags: Example: - Given: sptr[5:0] = 001010b POP This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b. .0 Format: POP R0 IDH // R0 HS[sptr-1], sptr sptr-1 // IDH HS[sptr-1], sptr sptr-1 In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction "POP IDH" load value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about POP operations for hardware stack. $0 Format: PUSH R0 IDH In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction "PUSH IDH" load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0] be emptied. Refer to chapter 5 for more detailed explanation about PUSH operations for hardware stack. $)$"$ Format: Operation: RET PC HS[sptr - 2], sptr sptr - 2 RET pops an address on the hardware stack into PC so that control returns to the subroutine call site. Flags: Example: - Given: sptr[5:0] = 001010b CALLS * * * Wait // Address at 00120h Wait: NOP NOP NOP NOP NOP RET // Address at 01000h After the first instruction CALLS execution, "PC+1", 0121h is loaded to HS[5] and hardware stack pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value 0121h on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became 001010b. () Format: RL () Format: RLC In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag. 0 Format: RR 0 Format: RRC In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC are used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag. $" Format: SBC Example: SBC SBC SUB SBC R0, 80h R0, R1 R0, R2 R1, R3 // If eid = 0, R0 R0 + ~DM[0080h] + C // If eid = 1, R0 R0 + ~DM[IDH:80h] + C // R0 R0 + ~R1 + C In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. Even if the result of "ADD R0, R2" is not zero, zero (Z) flag can be set to `1' if the result of "SBC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit addition, take care of the change of Z flag. )() Format: SL )() Format: Operation: Flags: SLA |